Research Assistant
Hardware Verification Group, Concordia University
● Developed neural network-based adder designs with various configurations (4-bit, 8-bit, 16-bit, 32-bit and 64-bit) in SV.
● Conducted reliability evaluations using META (Multi Event Transient Analysis) across various configurations.
● Demonstrated improved fault tolerance in neural network based digital circuit designs.
● Configured an advanced High-Performance Computing server with SLURM scheduler for optimized processing.
● Modified META tool's Python code to ensure compatibility with the SLURM scheduler.
● Automated the synthesis and places-and-route process in the ASIC design flow with python, tcsh and bash scripting.
● Worked with both 40nm and 65nm technology files.
ASIC Design Intern
● Underwent training in ASIC design flow, RTL coding and writing testbenches in Verilog. Gained knowledge on ADC, DAC, and communication interfaces (GPRS, M- Bus, RS485)
● Developed RTL code, wrote testbenches, and performed RTL and gate-level simulations to ensure reliable hardware for IoT applications.
● Facilitated daily Scrum meetings and reported task progress using Agile methodologies, ensuring timely delivery of design tasks.
● Managed Git repositories and utilized Linux OS and shell scripting to streamline development tasks and enhance productivity.